This lab exercise is ©2002 by Ren Colantoni. You are welcome to use it for any non-profit educational purpose to which it may apply. Just don't try to make money with it.

 

COMPUTER TECHNOLOGY 20
Laboratory Exercise 17 – JK Flip-Flops

OBJECTIVE: To observe the operation of a JK style flip-flop and compare it to a simple SC flip-flop.

MATERIALS: Elenco trainer; 7476 IC; hookup wire.

REFERNCES: Textbook, Chapter 5-6.

DISCUSSION: As we saw in the previous exercise, the traditional SET-CLEAR or SC flip-flop has an ambiguous state possible both inputs are in the high state when the clock pulse is applied. Both of the steering gates will attempt to control the NAND latch at the output of the circuit, and we will have no way of knowing how the circuit will react. We overcome this situation with the JK flip-flop, which has additional circuitry included that causes the flip-flop, when both inputs are high to toggle. This means that if the flip-flop has Q high and /Q low, the flip-flop will reverse conditions and end up with Q low and /Q high. Similarly, if the Q is initially low and /Q high, they will reverse polarity.

As you can see in the above figure, the toggling action of the JK flip-flop is created by a feedback line from the output of one of the NAND’s of the output latch to the opposing steering gate, which now becomes a 3-wide AND. This has the affect of allowing only one of the steering gates to be activated on any given clock pulse, and eliminates the ambiguous situation of both inputs are held high. The truth table for this circuit is:

J

K

CLK

RESULT

0

0

^

No change in state of circuit

0

1

^

Clears the circuit – Q = 0

1

0

^

Sets the circuit – Q =1

1

1

^

Toggles the output

In this exercise we will use the 7476 dual JK flip-flop which is common in many circuit designs. In addition to the circuitry discussed above, this part also provides a direct SET input and a direct CLR input for each of the two flip-flops in the package. These inputs allow the device to be SET or CLR’ed directly, without any concern for the state of the J or K inputs or the application of a clock pulse. This is a common option in many devices where we might want to reset a complete bank of flip-flops all at once or set one or more devices to a known given starting condition. You will need a specification sheet for the 7476 for this project.

PROCEDURE:

  1. Obtain a trainer and materials and set them up on the workbench in easy reach. Have your 7476 pin-out diagram handy.
  2. Examine the circuit below and note the following items:
    1. The CLK input to a 7476 JK flip-flop is using the negative-going edge of the clock pulse to cause the circuit to operate. This is in contrast to the flip-flop of the previous exercise that functions on the positive edge of the pulse.
    2. The direct SET and direct CLR inputs of the flip-flop are also activated by a low level. If you leave these floating, they will be ignored by the circuit. This isn’t a good idea, but we can make use of it in this exercise. The reason is that open inputs to a TTL circuit can act like antennas and be sensitive to ambient electrostatic noise in nearby circuits.
    3. There are, of course, two circuits in the device. Make sure you use the correct pin-outs for your circuit.

  1. Build the circuit on the trainer. Set all three switches to their down condition, then apply power.
  2. The line marked test probe in the diagram is really just a piece of hookup wire. We can use it to explore the operation of the direct SET and direct CLR functions. Place a piece of hookup wire into the correct row of holes on the protoboard of the trainer so that one end makes connection with the direct CLR pin of the flip-flop you are using in the IC. Then, touch the other end briefly to the GND pin of the trainer. This should turn the circuit off if it was on, with LED G off and LED H on.
  3. Next, remove the probe wire and move it to the direct SET pin of the same circuit. Again, touch the other end of the wire briefly to the GND pin. Result: ______________________________
    _____________________________________________________________________________
  4. Alternately use the probe to set and clear the device until you understand how these pins work. Leave the circuit in the SET condition, that is with LED G on.
  5. Next, we will test the operation of the circuit against truth table. Place both Data Switches (DS1 and DS2) in their down position if they are not already there. Then, briefly operate the LSX switch up and then down once. Result? __________________________________________________
  6. Next, place DS2, the K input, into the up position, and again operate the clock. Result?
    _____________________________________________________________________________
  7. Next, return the DS2 input to the down position and DS1, the J input, to the up position. Then, again operate the clock. Result? ______________________________________________________
  8. Finally, place both DS1 and DS2 to the up position, and operate the clock several times. Result?
    _____________________________________________________________________________

  1. With two devices in the same IC package, we can illustrate one common use of a flip-flop – that of dividing a clock pulse’s frequency by 2. This can be done several ways, depending upon what type of flip-flop we have available. Hook up the following circuit:
  2. In this circuit, we will use the LSX switch to act as our slow clock. Recall that the JK flip-flop operates on the low going edge of the clock pulse. So, every time we move the LSX up and down once, we will toggle the first flip-flop.

    The output of the first flip-flop is used as a clock to the second flip-flop. Again, this second device will operate on the low-going edge of its clock. So, how many operations of LSX will it take to run the second flip-flop through one complete set-reset cycle?
  3. First, apply a brief CLR pulse to both of the flip-flops in the circuit using a wire probe. Then, operate the LSX switch several times and record your readings in the table:

LSX CYCLE #

LED G

LED H

1

 

 

2

 

 

3

 

 

4

 

 

5

 

 

6

 

 

7

 

 

8

 

 
  1. From your readings you should be able to answer the question of step 13. How many LSX switch cycles are needed for one complete cycle of the second flip-flop? _______________________
    How many are needed for the first flip-flop? ______________________
  2. When you feel you have a good understanding of the JK flip-flop, remove power and disassemble the circuit. Return all parts and equipment to storage.

REVIEW QUESTIONS:

  1. Are there any ambiguous states in the operation of a JK flip-flop?
  2. Are the flip-flops of the 7476 device positive or negative edge triggered?
  3. Are the direct SET and direct CLR inputs of the 7476 flip-flops edge triggered or level triggered?
  4. Although we can allow the direct SET and direct CLR inputs of the flip-flops to be unconnected in this exercise, it is not a good idea to do this in a production system. Why?
  5. What do we mean when we say that a JK flip-flop toggles?